The present invention is directed to a system and method which ensure that the required number of refresh operations are performed to a memory during a wake-up period after powering on the memory by initializing the refresh count value. More particularly, the system and method compare the refresh count value to a predetermined threshold number and by initializing the refresh count value, the required number of refresh requests will be issued as high priority requests to ensure that the required number of refreshes is executed to the memory after powering on.
In conventional dynamic memory systems, the time that a node reliably stores a bit is referred to as the refresh period. The refresh period is based on the particular dynamic memory specifications. Since the charge stored on a dynamic node decays, it is necessary to sense and refresh the dynamic node within the refresh period. Therefore, dynamic memory systems are generally provided with a refresh circuit which generates a refresh request within the refresh period to ensure that the charge on the dynamic node does not decay and the bit remains reliably stored on the dynamic node.
An example of a known refresh operation for a dynamic memory system is illustrated in FIG. 1. A refresh circuit 10 generates refresh requests at predetermined intervals to the memory controller 20. The predetermined intervals are chosen to be within the refresh period to ensure that data on the dynamic node reliably remains. Conventionally, the predetermined intervals are about 15 .mu.sec. More specifically, the refresh circuit 10 generates an overflow signal at the end of the predetermined intervals. The generated overflow signals act as refresh requests which take priority before all of the other requests from an external processor (not shown). In these known systems, because the refresh requests take priority in the execution by the memory controller 20 before all of requests, the read latency is adversely affected due to the refreshes. For example, in the middle of a large block transfer, a read which conflicts with the refresh will be forced to wait until the refresh is completed because the refresh has priority. The amount of time necessary to complete the refresh is dependent upon the number of banks in the dynamic memory and thereby, the read latency becomes higher as the number of banks is increased.
FIG. 1 further illustrates a power unit 30 for powering on the memory controller 20. Upon powering on a dynamic memory, it is necessary to perform a wake-up operation where the dynamic memory does not operate for a certain amount of time and then a required number of refreshes are sequentially directed to the memory controller 20. Typically, the time period for which the dynamic memory does not receive requests is 200 .mu.sec and a number of refresh cycles is executed by the memory controller 20 for the wake-up operation. The required number of refresh cycles in the wake-up operation are executed so that the sense amplifiers of the dynamic memory are precharged. The required number of refreshes is set by the product's manufacturer and this number is typically 8 refresh cycles. However, in conventional memory controllers, it is usually assumed that the refresh cycles will occur during the reset interval but there is no circuitry for ensuring that the required number of refresh cycles will always occur.
To reduce the amount and complexity of circuitry used for the wake-up operation, it is desired to utilize other circuitry for more than one function for ensuring the required number of refresh cycles is performed. The embodiments of the present invention are directed to utilizing a refresh processor to ensure that the required number of refreshes are performed to a memory with simplified circuitry.